LCD having a capacitor with two lower capacitor electrodes and a reflective pixel electrode serving as an upper electrode

ABSTRACT

A thin film liquid crystal display, having a high aperture ratio, is described. The display has been designed so as to reduce the incidence of short circuits between its various parts. This has been achieved by modifying the structure of the lower electrode of the storage capacitor. The lower electrode is formed in the shape of a hollow square, two non-adjacent sides of the hollow square being at the level of the gate electrode, the other two sides of the hollow square being at the level of the data line. Two different means for providing electrical contact between all four sides of said lower capacitor electrode are described.

This application is a divisional application of 08/573,309 filed on Dec.15, 1995, now U.S. Pat. No. 5,657,101.

BACKGROUND OF THE INVENTION

(1) FIELD OF THE INVENTION

The invention relates to the general field of liquid crystal displays,more particularly, to the problem of providing a high aperture ratiowithout an increase in the complexity of the associated manufacturingprocess.

(2) DESCRIPTION OF THE PRIOR ART

FIG. 1 shows a schematic diagram of the circuit used to control aplurality of individual pixels, each comprising a Liquid Crystal (LC)device, arranged as an X-Y addressable array.

A layer of LC 1 is located between two electrodes, at least one of whichis transparent. One of said electrodes is grounded and the otherelectrode is connected to one of the scan lines 2 and to one of the datalines 3, thus making it uniquely addressable--it will not be activatedunless voltage is applied to both the appropriate scan and data linessimultaneously. Power to drive the LC is supplied by the data line butits availability is controlled from the scan line through Field EffectTransistor (FET) 5.

Additionally, a capacitor 4 is included with each pixel for the purposeof extending the time that the pixel is active beyond the very shorttime during which it receives voltage from both the scan and data linessimultaneously. This is analogous to using a long persistent phosphor ina cathode ray tube.

The physical implementation of the circuit diagrammed in FIG. 1 formsthe subject matter of the present invention. Problems that must beovercome in order to achieve a good implementation include improving theaperture ratio of the device, eliminating or reducing places whereshorting may occur between different parts of the structure, andproviding a cost effective process for its manufacture.

A conventional implementation, typical of the prior art, is shown inFIGS. 2(a) and (b), the former being a cross-section of the latterthrough 2a-2a. LC 15 is sandwiched between two glass substrates. Inaddition to Thin Film Transistor (TFT) 16, storage capacitor 11 has beenlocated at the same level as scan (or gate) line 14 to increase theopening of aperture 12. Capacitor layer 11 and black matrix layer 13combine to block out extraneous light. This structure has to allow forextra space to avoid the possibility of side-to-side shorting betweencapacitor 11 and scan line 14, since they are at the same level. Thisgoes counter to the requirement that space be limited in order toincrease pixel density (i.e. keep the pixel pitch small) so only alimited aperture ratio can be achieved with this structure.

FIG. 3(a) shows, in schematic cross-section, an example of an improvedapproach to the problem that has been described in the prior art byTakahashi et al. (`A high-aperture-ratio pixel structure forhigh-density a-Si TFT liquid crystal light valves' by N. Takahashi etal. the SID 93 digest pp. 610-613). In this structure, LC 15 iscontained between upper and lower glass plates 23 and 27 respectively.The gate electrode 20 and the storage capacitor 21 are located atdifferent levels. Light shields 21 are separated from FET control gate20 by insulating layer 24, the space between the light shields definingdevice aperture 25. This determines the amount of light that is allowedto pass through transparent electrode 26. This design requires thepresence of a second light shield 22 that is located on upper glassplate 23. FIG. 3(b) is a plan view of the structure of FIG. 3(a).

This structure allows more latitude in determining the size of aperture25 (in FIG. 3(a)) but it requires additional process steps relative toother known structures and, in particular, it requires the presence ofthe secondary light shield 22 in order to avoid illumination of the TFT.Continuing our reference to FIG. 3(a), scan line 20 and transparentpixel electrode 26 are located on the same side as common electrode 21,so the common electrode of storage capacitor 21 cannot be fully utilizedto block the electric field of the scan line. This causes some lightleakage 30 (in FIG. 3(c)) in one corner of the aperture, requiring lightshield 21 to have larger area.

Other prior art that relates to this area includes U.S. Pat. No.5,028,122 (July 1991) by Hamada et al. which describes overlapping thegate electrodes with the pixel electrodes so as to provide additionalcapacitance. This is not the problem solved by the present invention.

SUMMARY OF THE INVENTION

It has been an object of the present invention to provide a thin filmtransistor liquid crystal display having an improved aperture ratiobetween the transparent and opaque areas of the pixels.

A further object of the present invention has been to provide astructure that meets the first objective while at the same time reducingthe incidence of short circuits between the various parts that comprisesaid structure.

Another object of the present invention has been to provide a processfor manufacturing a thin film transistor liquid crystal display thatconforms to the first two objectives, said process to be no more costlythan similar processes already in use in the prior art.

These objects have been achieved by modifying the structure of the lowerelectrode of the storage capacitor. Said lower electrode is formed inthe shape of a hollow square, two non-adjacent sides of said hollowsquare being at the level of the gate electrode, the other two sides ofthe hollow square being at the level of the data line. Two differentmeans for providing electrical contact between all four sides of saidlower capacitor electrode are described. In the first, four via holesare formed at the four corners of the hollow square and material fromthe two layers that are at different levels make electrical contactthrough them. In the second, only two via holes, located at two adjacentcorners of the hollow square, are used, additional contact beingprovided by the overlap of the pixel electrode and the scan line.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of the circuit used to provide an X-Yaddressable array of liquid crystal devices.

FIGS. 2(a) and (b) show, in cross-section and plan respectively, atypical liquid crystal pixel structure that can be found in the priorart.

FIGS. 3(a) and (b) show a relatively recent improvement over the priorart of FIG. 2.

FIG. 3(c) shows the light leakage region in the absence of a blackmatrix.

FIGS. 4(a) through (e) show plan views of two embodiments of the presentinvention together with three appropriate cross-sections. Theseembodiments eliminate the need for a black matrix.

FIGS. 5(a) through (d) show a plan view of a third embodiment of thepresent invention together with three appropriate cross-sections. Thisembodiment requires the presence of a black matrix.

FIG. 6 is an isometric view of the lower (hollow square) capacitorelectrode.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring now to FIG. 4(a), we show there a cross-section illustratingthe inverted staggered TFT configuration, which is a feature of thepresent invention. First, a metal layer comprising a material such aschromium, tantalum or aluminum, and having a thickness between about 500and 4,000 Angstrom units, typically about 1,000 Angstroms, is depositedthrough sputtering (or similar deposition technique) onto glasssubstrate 41. Through lithography and etching, gate electrode 40 andfirst electrode 42 of the storage capacitor, located in the vicinity ofthe data lines, are formed.

Gate insulator layer 43, comprising silicon nitride, silicon oxide,aluminum oxide, or an anodic oxide and having a thickness between about1,000 and 5,000 Angstrom units, typically about 3,000 Angstroms, isformed on the upper surface of the glass substrate including the uppersurfaces of gate electrode 40 and storage electrode 42. A semiconductinglayer 44, comprising amorphous silicon and having a thickness betweenabout 300 and 3,000 Angstrom units, typically about 1,000 Angstroms, isformed on gate insulator layer 43. In order to electrically connect thedrain and source electrodes to semiconducting layer 44 a contactinglayer (not shown), comprising heavily doped amorphous silicon and havinga thickness between about 300 and 1,000 Angstrom units, typically about500 Angstroms, is formed on semiconducting layer 44. After lithographyand etching contact holes 6 (as shown in FIG. 4(b)) are formed forinterconnection purposes.

Next, a layer comprising a metal such as chromium, having a thicknessbetween about 1,000 and 6,000 Angstrom units, typically about 2,000Angstroms, is sputtered and patterned to form data line 49, source anddrain, and separated first electrode 46 of the storage capacitor,located around the region of the scan lines. This storage electrode 46connects with another storage electrode 42 through the contact holes 6to form a ring shape. In addition, a transparent insulating layer 47,comprising a material such as silicon nitride, silicon oxide, aluminumoxide, an anodic oxide, or a polyimide, is deposited on substantiallythe entire exposed surface.

The drain electrode 49 is then covered with capacitor dielectric layer47 to insulate it from other electrodes. The thickness of insulatinglayer 47 is between about 2,000 and 5,000 Angstrom units, typicallyabout 3,000 Angstroms. A through-hole extending through insulating layer47 is formed in a portion of layer 47 above the source electrode 49.Finally, a transparent conducting electrode 48, comprising Indium TinOxide (ITO), and having a thickness between about 500 and 3,000 Angstromunits, typically about 1,000 Angstroms, is formed on the upper surfaceof insulating layer 47. Transparent electrode 48 extends into thethrough-hole 8 and hence is electrically connected to source electrode49.

It is also possible for pixel electrode 48 to comprise an opaqueconductor. In such a case the embodiment would be for a reflective typeTFT Liquid Crystal Display.

FIGS. 4(a) through 4(e) illustrate various embodiments of the abovedescribed structure. FIG. 4(a) is cross-section 4a--4a in both of planviews 4(b) and 4(c) which show slightly different layouts for thestorage capacitor. In FIG. 4(c) the storage capacitor ring is completedby the overlap between the pixel electrode and the next scan line, soonly two contact holes are needed per cell. FIG. 4(d) is a section ofthe plan view shown in FIG. 4(b) taken along vertical line 4d--4d inFIG. 4(b). FIG. 4(e) is a section taken along a horizontal line 4c--4cin FIG. 4(b).

The present invention efficiently utilizes a single conducting layer toform the gate electrode (which is also the scan line) and thedrain/source layer (or data line) into a ring shaped storage capacitorthrough interconnection of the contact holes. This storage electrodeoverlaps scan line and data line. The combination of storage electrode,scan line, and data line serves the function of an integrated blackmatrix to avoid light leaks. This process is easier than the processillustrated in FIG. 3, for example. In the process that produces thestructure of FIG. 3, storage electrode 21 and insulator 24 representadditional steps in the process.

In the present invention, storage electrode 46 is set over scan line 40to shield the lateral field from the scan line voltage. So the effect ofthe lateral field of scan line 40 on the arrangement of the LC in thepixel electrode can be effectively avoided. Even if pixel electrode 48overlaps scan line 40, no parasitic capacitance is added. So theaperture ratio is efficiently increased and the problem of the lateralfield is greatly reduced.

FIGS. 5(a)-5(d) show another embodiment of the present invention. FIG.5(a) is a cross-section taken through 5a--5a in plan view FIG. 5(b).FIG. 5(c) is a cross-section of FIG. 5(b) taken along vertical line5c--5c. FIG. 5(d) is a cross-section of FIG. 5(b) taken along horizontalline 5d--5d. The process for forming this embodiment is the same as thatpreviously described in reference to FIG. 4, the difference being thatthe storage electrode 52 has been slightly separated from data line 59and storage electrode 56 slightly separated from scan lines 40, so ablack matrix 9 has been added to the upper glass to block light passingthrough the resulting gaps between storage electrode, data line and scanline. Compared with the conventional process, they have the same numberof process steps, but the gap spacing in the present invention betweenstorage electrode and scan line can be efficiently reduced sincestaggering different conducting layers onto different levels avoidsco-planar shorts. This makes possible the achievement of a higheraperture ratio.

To support our claim of greater efficiency for the structure of thepresent invention we note the following:

For the same pixel size, the aperture ratio associated with theembodiment of FIG. 4 is about 61% while that associated with theembodiment of FIG. 5 is about 53%. When using conventional structures ofthe prior art, such as that shown in FIG. 2, the aperture ratio is onlyabout 43%.

In order to help visualize the three dimensional appearance of thecapacitor, we show, in FIG. 6, an isometric projection of the lower(hollow square) electrode. The capacitor dielectric and the upperelectrode are both common to all capacitors of the display so are nowshown here.

While the invention has been particularly shown and described withreference to the preferred embodiments thereof, it will be understood bythose skilled in the art that various changes in form and details may bemade without departing from the spirit and scope of the invention.

What is claimed is:
 1. A thin film liquid crystal display comprising:afirst transparent insulating substrate upon whose surface are conductivescan and data lines, said scan and data lines being orthogonallydisposed relative to each other and electrically insulated from eachother; a thin film field effect transistor having a drain connected to adata line and a gate connected to the adjacent scan line; a thin filmcapacitor having a lower electrode in the shape of a hollow square, twonon-adjacent sides of said hollow square being at the level of said gateelectrode, the other two sides of the hollow square being at the levelof said data line; means for providing electrical contact between allfour sides of said lower capacitor electrode; an opaque, reflective,conductive layer that serves both as a pixel electrode and as an upperelectrode for said thin film capacitor; electrical connection betweensaid pixel electrode and a source region of said thin film field effecttransistor; electrical connection between said lower capacitor electrodeand a scan line once removed from the scan line to which said gate isconnected; and a layer of liquid crystal in contact with said pixelelectrode and kept in place by a transparent insulating substrate. 2.The structure of claim 1 wherein the means for providing electricalcontact between all four sides of said lower capacitor electrodecomprises four via holes, located at the four corners of the hollowsquare, through which material from the two layers that are at differentlevels make electrical contact.
 3. The structure of claim 1 wherein themeans for providing electrical contact between all four sides of saidlower capacitor electrode comprises two via holes, located at twoadjacent corners of the hollow square, and an overlap of said pixelelectrode and the scan line, through which material from the two layersthat are at different levels make electrical contact.
 4. The structureof claim 1 wherein said lower capacitor electrode and said scan lines donot overlap.
 5. The structure of claim 4 further comprising a blackmatrix electrode located on the surface of said second transparentinsulating substrate.